Live circuit monitoring

ABSTRACT

There are disclosed apparatus and methods for testing a live circuit powered from an alternating current (AC) voltage. A zero crossing detector detects zero crossings of the AC voltage. A spread spectrum time domain reflectometer (SSTDR) coupled to the zero crossing detector performs measurements of the live circuit, each measurement synchronized with a zero crossings of the AC voltage. A processor coupled to the SSTDR detects faults in the live circuit based on correlation data provided by the SSTDR.

NOTICE OF COPYRIGHTS AND TRADE DRESS

A portion of the disclosure of this patent document contains materialwhich is subject to copyright protection. This patent document may showand/or describe matter which is or may become trade dress of the owner.The copyright and trade dress owner has no objection to the facsimilereproduction by anyone of the patent disclosure as it appears in thePatent and Trademark Office patent files or records, but otherwisereserves all copyright and trade dress rights whatsoever.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 15/278,987filed on Sep. 28, 2016, titled ADAPTIVE LIVE CIRCUIT CHARACTERIZATION,the full contents of which are incorporated herein by reference.

BACKGROUND

Field

This disclosure relates to electrical system testing and particularly totesting electrical power distributions systems for intermittent faults.

Description of the Related Art

Electronic systems are ubiquitous. An essential component of thesesystems is their internal signal paths, most typically provided by wiredinterconnects. Failures in the wiring frequently result in failure ofthe system. For example, aging wiring in buildings, aircraft andtransportation systems, consumer products, industrial machinery, and thelike is among the most significant potential causes of catastrophicfailure and maintenance cost in these structures. High profile airlinecrashes attributed to aging wiring have brought the need for improvedwire testing systems to the forefront of industry attention.

Various techniques for the characterization and fault detection ofelectronic signal paths are known. For example, techniques such as timedomain reflectometry (TDR), frequency domain reflectometry (FDR), andsequence time domain reflectometry (STDR) can be used to determine wherea short or break in a wire has occurred. More recently, improvementssuch as spectral time domain reflectometry (STRDR) and spread spectrumtime domain reflectometry (SSTDR) have been developed to allow testingof a wire while operational signals are present. Common to all of thesetechniques is the injection of a reflectometry test signal into the wireto be tested, and observation of the response. As the test signalpropagates from the test instrument, impedance mismatches in the wiregenerate reflections that propagate back to the test instrument.Impedance mismatches can be caused by a variety of things, including forexample, breaks in the wire, short circuits, branches, and wire gaugechanges. The resulting response can be analyzed to determine features ofthe wire, such as distance to an open or short circuit.

Traditionally, reflectometry has been a form of off-line testing, sinceon-line live testing was avoided because the test signal may interferewith the existing power and/or signals on the line, and vice versa.Unfortunately, certain types of failures, such as an intermittentopen-circuit or short-circuit, are difficult to detect off-line, sincethe conditions causing the failure are often not present during off-linetesting.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a live circuit tester.

FIG. 2 is a timing diagram.

FIG. 3 is a flow chart of a process for monitoring a live circuit.

FIG. 4 is a flow chart of a process for reporting faults detected by alive circuit tested.

Throughout this description, elements appearing in figures are assignedthree-digit reference designators, where the most significant digit isthe figure number where the element is introduced and the two leastsignificant digits are specific to the element. An element that is notdescribed in conjunction with a figure may be presumed to have the samecharacteristics and function as a previously-described element havingthe same reference designator.

DETAILED DESCRIPTION

Description of Apparatus

Referring now to FIG. 1, a live circuit tester 100 may be insertedbetween an AC power source and a circuit under test to test the circuitfor intermittent and permanent shorts, opens, and other faults. Forexample, the live circuit tester 100 may be inserted in a breaker boxand connected between the circuit under test and the correspondingcircuit breaker 102.

The live circuit tester 100 includes a spread spectrum time domainreflectometer (SSTDR) 110, a zero crossing detector 130, an isolator140, a processor 150, a memory 160, a user interface 170, and a powersupply 180. The elements 110-180 of the live circuit tester 100 may becontained within a single physical unit, or may be distributed betweenmultiple units. For example, the isolator 140, which may be configuredto transmit high currents from the AC power source to loads within thecircuit under test, may be contained in a separate physical unit fromother elements of the live circuit tester.

The SSTDR 110 includes a timing generator 112, a code generator 114, aline interface 116, and a correlator 118. The timing generator 112synchronizes the operation of the other elements of the SSTDR 110. Thecode generator 114 generates a pseudorandom noise (pn) code. A pn codehas the characteristics of a random sequence of bits but isdeterministically generated using specialized circuits and/oralgorithms. The pn code from the code generator 114 is coupled onto theAC power line 105 via the line interface 116. The line interface 116 mayinclude a directional coupler, a circulator, or some other circuitelements to couple the pn code onto the AC power line 105 and to extractreflections of the pn code from the AC power line 105.

The pn code coupled onto the AC power line 105 propagates into thecircuit under test, but is prevented from propagating toward the ACpower source by the isolator 140. The isolator 140 may be an inductor orlow pass filter that blocks propagation of the pn code towards the ACpower source while transmitting AC power from the AC power source to thecircuit under test.

Each impedance discontinuity in the circuit under test will cause aportion of the energy of the pn code to reflect back to the SSTDR. Thereflected energy is separated from the AC power line 105 by the lineinterface 116. The separated reflected energy is input to the correlator118. The correlator 118 may be an analog or digital circuit thatcorrelates the reflected energy with a plurality of successively delayedcopies of the pn code generated by the code generator 114. Thecorrelator 118 outputs correlation data 120 to the processor 150. Thecorrelation data includes multiple data values representing thecorrelation of the reflected energy and the pn code delayed byrespective delay times. Each delay time represents a round-trip transittime from the SSTDR to a location within the circuit under test. Eachdelay time can be converted into a distance from the SSTDR to thecorresponding location within the circuit under test using a known orpresumed propagation velocity of the pn code over the circuit undertest. Thus each correlation data value represents an estimate of thedegree of impedance discontinuity (or lack thereof) at a point withinthe circuit under test located at a respective distance from the livecircuit tester 100. The distance from the live circuit tester 100 to animpedance discontinuity can be determined by interpolating betweenadjacent correlation data values.

The processor 150 includes hardware, which may be augmented by softwareand/or firmware, for providing functionality and features describedherein. The processor 150 may therefore include one or more of: logicarrays, memories, analog circuits, digital circuits, software, firmware,and processors such as microprocessors, field programmable gate arrays(FPGAs), application specific integrated circuits (ASICs), programmablelogic devices (PLDs) and programmable logic arrays (PLAs). The hardwareand firmware components of the processor 150 may include variousspecialized units, circuits, software and interfaces for providing thefunctionality and features described here. The processes, functionalityand features may be embodied in whole or in part in software executed bythe hardware of the processor 150. This software may be in the form offirmware, an application program, an applet (e.g., a Java applet), abrowser plug-in, a COM object, a dynamic linked library (DLL), a script,one or more subroutines, or an operating system component or service.The hardware and software and their functions may be distributed suchthat some components are performed by the processor 150 and others byother devices.

The memory 160 may include read only memory (ROM), random access memory(RAM), flash memory or other nonvolatile memory, or a combinationthereof. The memory 160 may store program instructions for execution bythe processor. The memory 160 may also store data such as correlationdata and intermediate and final results of processes performed upon thecorrelation data.

The processor 150, in combination with the memory 160, may process thecorrelation data 120 from the SSTDR 110 to detect potential faultswithin the circuit under test. A fault, such as a short or an opencircuit, will cause an impedance discontinuity resulting in a reflectionof pn code energy back towards the SSTDR. The reflected pn code energywill result in an elevated value of one or more of the correlation datavalues 120. However, every substantial load within the circuit undertest is also an impedance discontinuity that reflects pn code energyback towards the SSTDR. Thus not all elevated correlation data valuesare caused by faults.

To distinguish faults, the processor may establish and store acorrelation data baseline 162. The correlation data baseline 162 may bea set of baseline correlation values representing the expectedcorrelation data values resulting from reflections from the circuitunder test when the circuit under test is operating normally. Thecorrelation data baseline 162 may be established, for example, as anaverage of multiple sets of correlation data values. Faults may then bedetected by comparing correlation data values 120 received from thecorrelator 118 with the baseline 162 stored in the memory 160. Asignificant difference between one or more of the real-time correlationvalues and the corresponding baseline values may indicate a fault at thecorresponding distance from the live circuit tester 100. Each detectedfault may be stored in a fault list 164 in the memory 160.

Certain types of faults in the circuit under test may be intermittentand dynamic. For example, an intermittent short or open may arc onlyduring a portion of each half-cycle of the AC line voltage. Such dynamicfaults may cause a significant change in impedance during some or allhalf cycles of the AC line voltage. Such an impedance change occurringwhile the correlator 118 is correlating reflected energy from the lineinterface 116 with delayed copies of the pn code from the code generator114 can result in errors in the correlation data 120. Such errors maycause the processor 150 to misinterpret the correlation data such that afault is not detected, or a detected fault is estimated to be in anincorrect location.

To provide consistent correlation data in the presence of intermittentfaults, the live circuit tester 100 may synchronize the activity of thecorrelator 118 with zero-crossings of the AC line voltage. To this end,the live circuit tester 100 includes a zero crossing detector 130 thatprovides a zero crossing signal 132 to the timing generator at each zerocrossing of the AC line voltage. The timing generator uses the zerocrossing signal 132 to synchronize the operation of the correlator 118such that correlations are performed only during a correlation timewindow proximate to the zero crossing of the AC line voltage. Forexample, the correlation time window may begin at the zero crossing ormay be centered upon the zero crossing, or synchronized to the zerocrossing in some other manner. In any case, the correlation time windowmay be short compared to the period of the AC line voltage such thatcorrelations are performed while the AC voltage is less than apredetermined threshold voltage. The predetermined threshold voltage maybe, for example, an estimate of a voltage level where arcing occurs inthe circuit under test. The code generator 114 may run continuously ormay also be synchronized with the zero crossing of the AC line voltage.

FIG. 2 is a timing diagram illustrating (A) the AC line voltage, (B) thezero crossing signal 132, (C) a correlation time window starting at eachzero crossing, and (D) an alternative correlation time window centeredupon each zero crossing. In this example, the correlation time windows(C) and (D) occur while the AC line voltage (A) is less than 40% of itsmaximum value. The duration of the correlation time windows may begreater than or less than the windows shown in this example, such thatthe maximum AC line voltage during each correlation time window is morethan or less than 40% of its maximum value. The window is shorter thanone-half cycle of the AC line voltage, and may be less than one quartercycle.

Referring again to FIG. 1, the circuit under test may include dynamicloads that switched on and off during normal operation. Examples ofdynamic loads include elevator and air conditioning motors, banks oflights, high power industrial equipment such as ovens and arc welders,and other equipment. Switching a dynamic load on or off will cause acorresponding change in the impedance of the circuit under test. Thecorrelation data 120 produced immediately after switching a dynamic loadmay differ from the baseline 162 sufficiently to be incorrectly detectedas a fault.

To avoid repeated detection of dynamic loads, an ignore table 166 may bestored in the memory 160. The ignore table 166 may store one or moreignore values defining the location of known dynamic loads. The one ormore ignore values may be stored as the distance from the live circuittester to the corresponding dynamic load. The one or more ignore valuesmay be stored as the round-trip transit time from the live circuittester to the corresponding dynamic load. The one or more ignore valuesmay be stored in some other form sufficient to identify the location ofthe corresponding dynamic load.

Upon detection of a potential fault in the circuit under test, theprocessor 150 compares an estimated location of the potential fault withthe locations identified in the ignore table 166. A potential fault thatmatches a location identified in the ignore table 164 will be ignored,which is to say a potential fault that matches the location of a knowndynamic load is not reported to a user of the live circuit tester. Apotential fault that matches a location identified in the ignore table166 may not be ignored if switching the dynamic load trips the circuitbreaker 102, disconnecting the live circuit tester and the circuit undertest from the AC power source.

The user interface 170 includes a display element 172 and a data inputelement 174. The display element 172 may include one or more displaydevices such as a liquid crystal display or other flat panel displaydevice. The display device may be configured to display the distance to,and type of, a detected fault. The display element 172 may also beconfigured to display additional information such as a batter chargelevel, a test in progress indicator, and/or the duration of an ongoingor completed test. The display element 172 may optionally include one ormore indicator lights, for example to indicate when the live circuittester is connected to an AC line, when a test is in progress, and/orwhen a fault has been detected.

The data input element 174 may include one or more data entry buttons orkeys, a touch screen integrated with the display device, or acombination of a touch screen and one or more mechanical buttons orkeys. For example, the data input element 174 may include a “test”button to start and stop tests, a “display” button to cause the livecircuit tester to display the location and type of a detected fault (orthe next detected fault when more than one fault has been detected), andan “ignore” button to instruct the live circuit tester to ignore thepresently displayed fault. When the data input element 174 is orincludes a touch screen, these buttons may be virtual buttons presentedon the display element 172.

The live circuit tester 100 may commonly operate unattended for periodsof time ranging from minutes to days. Each fault detected during anunattended test may be stored in the fault list 164 and subsequentlydisplayed in response to an operator request via the user interface 170.

The power supply 180 provides operational power for the other elementsof the live circuit tester 100. The power supply may receive input powerfrom the AC line 105 and convert the AC line voltage into one or more DCvoltages to power the other elements of the live circuit tester. AC linevoltage may be tapped while conducting a test, or during non-test timesand stored for test times. The power supply 182 may include or becoupled to a battery 182. The battery may provide a constant powersource, or may provide operating power to the other elements of the livecircuit tester 100 in the event the circuit breaker 102 is trippedduring a test. The battery enables the live circuit tester 100 to storeand display faults after the circuit breaker 102 is tripped or when thelive circuit tester 100 is otherwise disconnected from the AC powersource.

Description of Processes

Referring now to FIG. 3, a process 300 for testing a live circuit usinga live circuit tester, such as the live circuit tester 100, starts at305. The process 300 normally ends at 395 after completion of a test, ormay end prematurely at 390 if the testing results in a circuit breakertrip. The process 300 is cyclical in nature with the activities from 315to 355 repeated every half-cycle of the AC line voltage.

At 310, the live circuit tester is installed, which is to say the livecircuit tester is interposed between an AC power source and the circuitto be tested. For a typical test, the live circuit tester may betemporarily disposed with a circuit breaker box and connected betweenthe circuit to be tested and the load side of the corresponding circuitbreaker. Installation typically involves disconnecting one or two wiresfrom the circuit breaker, reconnecting the disconnected wires to theload side of the live circuit tested, and installing one or two jumperwires between the live circuit tester and the circuit breaker.

At 315, an SSTDR measurement of the circuit under test is performed.Performing an SSTDR measurement includes generating a pn code,transmitting the pn code over the circuit under test, receivingreflections of the pn code energy from the circuit under test, andcorrelating the reflected pn code energy with delayed copies of the pncode. The result of an SSTDR measurement is a set of correlation datavalues representing the correlation of the reflected energy and the pncode delayed by respective delay times. Each delay time represents around-trip transit time from the live circuit tester to a locationwithin the circuit under test. Each delay time can be converted into adistance from the live circuit tested to the corresponding locationwithin the circuit under test using a known or presumed propagationvelocity of the pn code over the circuit under test. Thus eachcorrelation data value represents an estimate of the degree of impedancediscontinuity (or lack thereof) at a point within the circuit under testlocated at a respective distance from the live circuit tester. Each setof correlation data values may be considered as a vector C(t), whereeach element in the vector C(t) is the correlation of correlation of thereflected energy and the pn code delayed by a respective delay time.

Each SSTDR measurement performed at 315 may be synchronized with a zerocrossing of the AC line voltage. Specifically, correlating the reflectedpn code energy with delayed copies of the pn code may be performed in acorrelation window synchronized with a zero crossing of the AC linevoltage. For example, each correlation window may start at a zerocrossing, as shown in FIG. 2(C), or may be centered upon a zerocrossing, as shown in FIG. 2(D). Each correlation window may besynchronized with the zero crossing of the AC line voltage in some othermanner. SSTDR measurements at 315 may be repeated at every zero crossingof the AC line, or at a rate of 100 or 120 measurements per seconddepending on the frequency of the AC line voltage. SSTDR measurements at315 may be repeated at a slower rate, such as every second or everythird every zero crossing of the AC line.

A baseline for the correlation data is established at 320. Thecorrelation data baseline at time t may be considered as a vector B(t),where t is measured in SSTDR measurement intervals, which may be halfcycles of the AC line voltage. Each element in the vector B(t) is thebaseline value, or expected value, of the correlation of the reflectedenergy and the pn code delayed by a respective delay time. At 320, thecorrelation data baseline B(0) may be determined by summing orintegrating correlation data from a plurality of consecutive SSTDRmeasurements. The correlation data baseline B(0) may be established, forexample, by calculating a moving average of n sets of correlation datavalues, as follows:

$\begin{matrix}{{B(0)} = {\frac{1}{n}{\sum\limits_{i = 1}^{n}{C\left( {- i} \right)}}}} & (1)\end{matrix}$where B(0) is the correlation data baseline at the current time (t=0),C(−1) is the correlation data vector from the previous SSTDRmeasurement, C(−i) is the correlation data from the i^(th) previousSSTDR measurement, and n is an integer greater than one. Alternatively,the correlation data baseline may be determined at 320 as a decayingintegral of the correlation data, as follows:B(0)=x C(0)+(1−x)B(−1)  (2)where B(0) is the correlation data baseline at the current time (t=0),C(0) is the correlation data vector from the current SSTDR measurement,B(−1) is the correlation data baseline at time of the previous SS TDRmeasurement, and x is decay constant between zero and one. Thecorrelation data baseline may be determined at 320 in some other manner.

At 325 a determination may be made whether or not the circuit breakertripped during or since the previous SSTDR measurement. A circuitbreaker is indicated by a loss of power on the AC line (105 in FIG. 1)accompanied by automatically switching to battery power for theoperation of the live circuit tester. When the circuit breaker hastripped (“yes” at 315), the correlation data may be stored at 330 fordiagnostic purposes and the test may end at 390.

When the circuit breaker has not tripped (“no” at 325), the process 300continues at 335. At 335, the correlation data vector from the mostrecent SSTDR measurement at 315 is compared to the correlation databaseline from 320. The comparison may be performed, for example, bysubtracting each element of the correlation data vector from thecorresponding element of the correlation data baseline. Potential faultsmay be indicted by differences between corresponding elements of thecorrelation data vector and the correlation data baseline.

The comparison results from 335 are screened at 340 to identify faults.In this context, “screened” has its conventional definition of “examinedmethodically in order to make a separation into different groups.” Inthis case, the correlation data is examined to distinguish differencesbetween the correlation data vector and the correlation data baselinedue to noise and routine variations in the circuit under test (i.e.non-faults), and differences due to faults in the circuit under test.One or more screening criteria may be used to distinguish faults fromnon-faults. For example a difference between corresponding elements ofthe correlation data vector and the correlation data baseline may beconsidered a fault only if the magnitude of the difference exceeds afirst predetermined threshold. A difference between correspondingelements of the correlation data vector and the correlation databaseline may be considered a fault only if the difference persists formultiple consecutive SSTDR measurements, such as three consecutivemeasurement or five consecutive measurements. A difference betweencorresponding elements of the correlation data vector and thecorrelation data baseline may be considered a fault only if thedifference persists for n consecutive SSTDR measurements, where n is apredetermined integer number greater than one. A difference betweencorresponding elements of the correlation data vector and thecorrelation data baseline may be considered a fault only if the total ofthe differences summed over a predetermined number of consecutive SSTDRmeasurements exceeds a second predetermined threshold. Other screeningcriteria may be used to distinguish faults and non-faults in additionto, or instead of, these example criteria.

At 345, a determination is made whether or not the screening at 340identified one or more faults. If a determination is made that no faultshave been detected (“no” at 345), the process 300 proceeds to 350, wherea determination is made whether or not an instruction to end the testhas been received. An instruction to end the test may be received, forexample, from an operator using a physical or virtual “test” button onthe live circuit tester. When an instruction to end the test has beenreceived (“yes” at 350), the testing process ends at 395. Any fault datastored during the test is retained and may be displayed after theconclusion of the test. When an instruction to end the test has not beenreceived (“no” at 350), the process 300 returns to 315 to performanother SSTDR measurement. The actions from 315 to 350 repeat cyclicallyuntil the test is ended by a circuit breaker trip or operator action.

When a determination is made at 345 that a fault has been detected(“yes” at 345), a determination may be made at 355 whether or not thedetected fault should be ignored. As previously discussed, the circuitunder test may include dynamic loads that switch on and off duringnormal operation. Switching a dynamic load on or off will cause a changein the impedance of the circuit under test at the location of thedynamic load and a corresponding change in the correlation data producedby the SS TDR measurements. When a dynamic load is switched andmaintained in its new state (i.e. either on or off) for a prolongedperiod, a new correlation data baseline is automatically established at320. Depending on the method used to establish the correlation atbaseline, the transition from the old correlation data baseline to thenew correlation data baseline may occur over an extended time period.SSTDR measurements performed immediately after switching a dynamic loadand during the correlation baseline transition period may result in thedynamic load being incorrectly identified as a fault at 345.

To avoid repeated detection of dynamic loads, one or more ignore valuesdefining the location of known dynamic loads or other prospective faultsmay be stored in an ignore table in the memory of the live circuittester. The one or more ignore values may be stored as the distance fromthe live circuit tester to the corresponding dynamic load or theround-trip transit time from the live circuit tester to thecorresponding dynamic load. The one or more ignore values may be storedin some other form sufficient to identify the location of thecorresponding dynamic load.

When a determination is made at 345 that a fault has been detected, alocation of the fault (which may be expressed as a distance and/or roundtrip transit time to the prospective fault) is derived from thecorrelation data. At 355, the location of the prospective fault iscompared to locations stored in the ignore table. A prospective faultthat matches a location identified in the ignore table is ignored (“yes”at 355), which is to say the location and type of the prospective faultare not stored in memory and are not subsequently reported to the testoperator. A prospective fault that does not match a location stored inthe ignore table (“no” at 355) is stored in memory for later reportingto the operator. In either case, the process 300 continues from 350 aspreviously described.

FIG. 4 is a flow chart of a process 400 for reporting faults detected bya live circuit tester such as the live circuit tester 100. The process400 begins at 405 and may optionally end at 495. The process 400 iscyclic in nature and the actions from 410 to 440 may be repeated foreach fault detected by the live circuit tester during a test session.Each cycle through the process 400 results in one detected fault to bereported. When more than one fault has been detected, the faults may besequentially reported in the order detected, in the order of increasingdistance from the live circuit tester, or in some other order.

The process 400 may be performed during a test session, or after a testsession is terminated by an operator action or a circuit breaker trip.The process 400 may be initiated at 405 by an operator action, such aspressing a physical or virtual key on the live circuit tester. The keyused to initiate the process 400 may be, for example, a display commandkey used to request display of a fault.

After the process 400 is initiated at 405, an optional determinationwhether or not there are more faults to be reported may be made at 410.On the first cycle though the process 400, immediately after the process400 is initiated, the determination at 410 will be whether or not thereare any faults at all to be reported. On subsequent cycles through theprocess 400, the determination at 410 will be whether or not there areany additional faults that have not yet been reported. When there are nomore faults to report (“no” at 410) the process 400 may end at 495.

When a determination is made at 450 that there are more faults to bereported (“yes” at 450), a next fault is displayed on a display deviceof the live circuit tester at 420. The information displayed at 420 mayinclude, for example, a distance to the fault and whether the fault is ashort or an open. Additional information, such as whether a fault isintermittent, persistent, or arcing may also be displayed.

After the next fault is displayed at 420, the process 400 may wait forreceipt of either an ignore command or a display command. Either ofthese commands may be received from an operator via respective physicalor virtual keys on the live circuit tested. In FIG. 4, waiting for oneof these commands is represented as an idle loop between the actions at430 and 440. Alternative implementations are possible. For example, theprocess 400 may be paused and subsequently resumed by an interruptindicating either a display command or an ignore command has beenreceived.

Receipt of an ignore command indicates the operator does not want futuredetections of the display fault to be reported. This may typicallyhappen when the displayed “fault” is false detection resulting fromswitching a dynamic load within the circuit under test. When an ignorecommand is received (“yes” at 430) the location of the currentlydisplayed fault is saved at 460. For example, the location of thecurrently displayed fault may be saved in an ignore table in memorywithin the live circuit tester. After saving the fault to be ignored,the process 400 may return to the idle loop 430/440 to wait for receiptof a display command. When a display command is received (“yes” at 440),the process 400 repeats from 410. Since the ignore command stores thelocation of the currently displayed fault, an ignore command, whendesired, must be entered before the next display command.

When the optional action at 410 is not implemented in the process 400,initiation of the process at 450 causes a first fault to be display at420. Receipt of a display command at 440 causes the next fault to bedisplayed at 420. When only one fault has been detected, that one faultmay be displayed continuously. When multiple faults have been detected,the display will repeatedly cycle through the faults in sequence inresponse to display commands. When the optional action at 410 is notimplemented in the process 400, the process 400 may continueperpetually, or until stopped by an event such as expiration of atimeout period or an operator action, neither of which is shown in FIG.4.

Closing Comments

Throughout this description, the embodiments and examples shown shouldbe considered as exemplars, rather than limitations on the apparatus andprocedures disclosed or claimed. Although many of the examples presentedherein involve specific combinations of method acts or system elements,it should be understood that those acts and those elements may becombined in other ways to accomplish the same objectives. With regard toflowcharts, additional and fewer steps may be taken, and the steps asshown may be combined or further refined to achieve the methodsdescribed herein. Acts, elements and features discussed only inconnection with one embodiment are not intended to be excluded from asimilar role in other embodiments.

As used herein, “plurality” means two or more. As used herein, a “set”of items may include one or more of such items. As used herein, whetherin the written description or the claims, the terms “comprising”,“including”, “carrying”, “having”, “containing”, “involving”, and thelike are to be understood to be open-ended, i.e., to mean including butnot limited to. Only the transitional phrases “consisting of” and“consisting essentially of”, respectively, are closed or semi-closedtransitional phrases with respect to claims. Use of ordinal terms suchas “first”, “second”, “third”, etc., in the claims to modify a claimelement does not by itself connote any priority, precedence, or order ofone claim element over another or the temporal order in which acts of amethod are performed, but are used merely as labels to distinguish oneclaim element having a certain name from another element having a samename (but for use of the ordinal term) to distinguish the claimelements. As used herein, “and/or” means that the listed items arealternatives, but the alternatives also include any combination of thelisted items.

It is claimed:
 1. Apparatus for testing a live circuit powered from analternating current (AC) voltage, comprising: a zero crossing detectorto detect zero crossings of the AC voltage; a spread spectrum timedomain reflectometer (SSTDR) coupled to the zero crossing detector, theSSTDR configured to perform measurements of the live circuit, eachmeasurement synchronized with a zero crossing of the AC voltage detectedby the zero crossing detector; and a processor coupled to the SSTDR andconfigured to detect faults in the live circuit based on correlationdata provided by the SSTDR.
 2. The apparatus of claim 1, where the SSTDRperforms measurements of the live circuit by generating a pseudo-noise(pn) code; transmitting the pn code over the live circuit, andgenerating the correlation data by correlating reflections received fromthe live circuit with a plurality of successively delayed copies of thepn code, the correlating performed only during periodic correlationwindows synchronized to zero crossings of the AC voltage.
 3. Theapparatus of claim 2, wherein each of the periodic correlation windowsstarts at a zero crossing of the AC voltage.
 4. The apparatus of claim2, wherein each of the periodic correlation windows is centered on azero crossing of the AC voltage.
 5. The apparatus of claim 2, whereingenerating and transmitting the pn code is performed continuously. 6.The apparatus of claim 2, wherein generating and transmitting the pncode is performed only during the periodic correlation windows.
 7. Theapparatus of claim 1, wherein the processor determines a correlationbaseline by integrating correlation data from a plurality of consecutiveSSTDR measurements, and the processor detects faults in the live circuitbased on a comparison of the correlation data and the correlationbaseline.
 8. The apparatus of claim 7, wherein the correlation dataconsists of a plurality of correlation values, each representing acorrelation of the reflections with a copy of the pn code delayed by arespective delay time, and the correlation baseline consists of aplurality of baseline values, each representing an expected value of thecorresponding correlation value.
 9. The apparatus of claim 8, whereinthe processor detects a fault in the live circuit if one or more of thecorrelation values differs from the corresponding baseline value by morethan a predetermined threshold.
 10. The apparatus of claim 8, whereinthe processor detects a fault in the live circuit if one or more of thecorrelation values differs from the corresponding baseline value by morethan a predetermined threshold for n consecutive SSTDR measurements,where n is an integer greater than
 1. 11. A method for testing a livecircuit powered from an alternating current (AC) voltage, comprising:detecting zero crossings of the AC voltage; performing spread spectrumtime domain reflectometer (SSTDR) measurements of the live circuit, eachSSTDR measurement synchronized with a detected zero crossing of the ACvoltage; and detecting faults in the live circuit based on correlationdata resulting from the SSTDR measurements.
 12. The method of claim 11,wherein performing SSTDR measurements further comprises: generating apseudo-noise (pn) code; transmitting the pn code over the live circuit,and generating the correlation data by correlating reflections receivedfrom the live circuit with a plurality of successively delayed copies ofthe pn code, the correlating performed only during periodic correlationwindows synchronized to zero crossings of the AC voltage.
 13. The methodof claim 12, wherein each of the periodic correlation windows starts ata zero crossing of the AC voltage.
 14. The method of claim 12, whereineach of the periodic correlation windows is centered on a zero crossingof the AC voltage.
 15. The method of claim 12, wherein generating andtransmitting the pn code is performed continuously.
 16. The method ofclaim 12, wherein generating and transmitting the pn code is performedonly during the periodic correlation windows.
 17. The method of claim11, further comprising: determining a correlation baseline byintegrating correlation data from a plurality of consecutive SSTDRmeasurements, and detecting faults in the live circuit based on acomparison of the correlation data and the correlation baseline.
 18. Themethod of claim 17, wherein the correlation data consists of a pluralityof correlation values, each representing a correlation of thereflections with a copy of the pn code delayed by a respective delaytime, and the correlation baseline consists of a plurality of baselinevalues, each representing an expected value of the correspondingcorrelation value.
 19. The method of claim 18, wherein detecting faultsin the live circuit further comprises: detecting a fault in the livecircuit if one or more of the correlation values differs from thecorresponding baseline value by more than a predetermined threshold. 20.The method of claim 18, wherein detecting faults in the live circuitfurther comprises: detecting a fault in the live circuit if one or moreof the correlation values differs from the corresponding baseline valueby more than a predetermined threshold for n consecutive SSTDRmeasurements, where n is an integer greater than 1.